1. Field of the Invention
The present invention relates to the field of integrated circuits and more particularly to excessive capacitive loading remediation for integrated circuits and printed circuit board (PCB) structures.
2. Description of the Related Art
Among the most advanced integrated circuits (IC), microprocessors control everything from computers to cellular phones to the digital processing of microwaves. The various computational processes and programmatic operations performed by microprocessors are facilitated through the use of signals that provide electrical pathways for data to propagate between the various components of an IC. ICs have consistently migrated to smaller feature sizes over the years, allowing more circuitry to be packed on each chip.
Communication links between ICs typically have long, interconnected electrical wiring inherently exhibiting significant delays to rise and fall times based on the resistance and capacitance of the electrical wiring. All electrical wiring in ICs has some amount of resistance and some amount of capacitance, although it is generally minimized by designing ICs with the shortest possible routes and maximum isolation from other wiring. The edges of digital signals have exponentially rising and falling edges which, combined with this resistance and capacitance of the electrical wiring inside ICs and PCB traces, lead directly to significant propagation delays. This propagation delay slows the falling edge of a signal, consequently leading to an excessive fall time. This excessive transmission line bus capacitance, which causes propagation delay, can also lead to poor signal quality.
Excessive bus capacitance often arises in the context of driving a universal serial bus (USB) interface from the motherboard of a personal computer. Referring to FIG. 1A, a schematic illustration is provided of a computing system configured to support a conventional USB interface as known in the art. As shown in FIG. 1A, the host computing platform 110 can generally support USB devices 140 through a USB port driver 150 that couples to a host controller driver 120 over a USB bus 130. The signal shared between the host controller driver 120 and the USB port driver 150 can become susceptible to excessive bus capacitance due to its overall length.
Conventional options for combatting excessive bus capacitance include rise time accelerators that attempt to decrease the excessive bus capacitance in a transmission line. However, these rise time accelerators only affect the rising edge of a signal and not the falling edge of a signal. A second option to counteract excessive capacitance in medium speed devices is to implement shorter cable runs but that could place severe limits on the applications by restricting the length of the bus to an impractical length. A third option is to apply re-clocking or re-driving. As yet a fourth option, signal propagation delay time can be reduced by making line driving transistors large. However, the enlargement of transistors of individual output gates requires extremely large area and therefore an increased size in the chip. An unfavorable result of overall increase in power consumption can occur as a result.
One conventional solution to improve adverse effects on signal timings and propagation delays includes the placement of buffers in series along the wiring route. Specifically, an otherwise long wiring route can be broken into two parts, and two inverters forming buffers can be placed serially there between. However, the breaking of the electrical wiring route into two parts increases the overall delay of the signal. Moreover, since the wiring route is physically cut into two parts, a contact resistance is added to the circuit because of contacts with the cut portions. The USB Bus, however, is bidirectional such that this approach requires bidirectional buffers. This additional requirement increases complexity in the control circuit required to determine the direction of drive. These and other factors increase propagation delays even further.